Virtual wires : overcoming pin limitations in FPGA-based logic emulation /
Abstract: "Existing FPGA-based logic emulators are limited by inter-chip communication bandwidth, resulting in low gate utilization (10 to 20 percent of usable gates). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulati...
Main Author: | |
---|---|
Format: | Thesis Book |
Language: | English |
Published: |
Cambridge, Mass. :
Massachusetts Institute of Technology. Laboratory for Computer Science,
[1993]
|
Series: | Technical report (Massachusetts Institute of Technology. Laboratory for Computer Science) ;
MIT/LCS/TR-586 |
Subjects: |