Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits /
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| Format: | Book |
| Language: | English |
| Published: |
Cambridge, Mass. :
Massachusetts Institute of Technology, Microsystems Program Office,
1990
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| Series: | VLSI memo ;
595 |
| Subjects: |
Internet
This item is not available through BorrowDirect. Please contact your institution’s interlibrary loan office for further assistance.Massachusetts Institute of Technology
| Call Number: |
TK7874.I5423 no.90- 595 |
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