Introduction to reconfigurable computing : architectures, algorithms, and applications /

Introduction to reconfigurable computing : architectures, algorithms, and applications /

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Bibliographic Details
Main Author: Bobda, Christophe
Other Authors: Hartenstein, Reiner
Format: Book
Language:English
Published: Dordrecht : Springer, c2007
Dordrecht : Springer-Verlag, c2007
Subjects:
Adaptive computing systems
Field programmable gate arrays
Programmable array logic
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245 1 0 |a Introduction to reconfigurable computing :  |b architectures, algorithms, and applications /  |c by Christophe Bobda 
260 |a Dordrecht :  |b Springer,  |c c2007 
260 |a Dordrecht :  |b Springer-Verlag,  |c c2007 
300 |a xxiv, 359 p. :  |b ill. ;  |c 25 cm 
336 |a text  |b txt  |2 rdacontent 
337 |a unmediated  |b n  |2 rdamedia 
338 |a volume  |b nc  |2 rdacarrier 
500 |a On cover: foreword by Reiner Hartenstein 
500 |a This WorldCat-derived record is shareable under Open Data Commons ODC-BY, with attribution to OCLC  |5 CTY 
504 |a Includes bibliographical references (p. [319]-335) and index  |t Managing the Device's Occupied Space --  |g 5.  |t Conclusion --  |g 6.  |t Online Communication --  |g 1.  |t Direct Communication --  |g 2.  |t Communication Over Third Party --  |g 3.  |t Bus-based Communication --  |g 4.  |t Circuit Switching --  |g 5.  |t Network on Chip --  |g 6.  |t The Dynamic Network on Chip (DyNoC) --  |g 7.  |t Conclusion --  |g 7.  |t Partial Reconfiguration Design --  |g 1.  |t Partial Reconfiguration on Virtex Devices --  |g 2.  |t Bitstream Manipulation with JBits --  |g 3.  |t The Modular Design Flow --  |g 4.  |t The Early Access Design Flow --  |g 5.  |t Creating Partially Reconfigurable Designs --  |g 6.  |t Partial Reconfiguration using Handel-C Designs --  |g 7.  |t Platform design --  |g 8.  |t Enhancement in the Platform Design --  |g 9.  |t Conclusion --  |g 8.  |t System on a Programmable Chip --  |g 1.  |t Introduction to SoPC --  |g 2.  |t Adaptive Multiprocessing on Chip --  |g 3.  |t Conclusion --  |g 9.  |t Applications --  |g 1.  |t Pattern Matching --  |g 2.  |t Video Streaming --  |g 3.  |t Distributed Arithmetic --  |g 4.  |t Adaptive Controller --  |g 5.  |t Adaptive Cryptographic Systems --  |g 6.  |t Software Defined Radio --  |g 7.  |t High-Performance Computing -- 
504 |a Includes bibliographical references (p. [319]-335) and index 
505 0 0 |g 1  |t Introduction --  |g 1.  |t General Purpose Computing --  |g 2.  |t Domain-Specific Processors --  |g 3.  |t Application-Specific Processors --  |g 4.  |t Reconfigurable Computing --  |g 5.  |t Fields of Application --  |g 6.  |t Organization of the Book --  |g 2.  |t Reconfigurable Architectures --  |g 1.  |t Early Work --  |g 2.  |t Simple Programmable Logic Devices --  |g 3.  |t Complex Programmable Logic Device --  |g 4.  |t Field Programmable Gate Arrays --  |g 5.  |t Coarse-Grained Reconfigurable Devices --  |g 6.  |t Conclusion --  |g 3.  |t Implementation --  |g 1.  |t Integration --  |g 2.  |t FPGA Design Flow --  |g 3.  |t Logic Synthesis --  |g 4.  |t Conclusion --  |g 4.  |t High-Level Synthesis for Reconfigurable Devices --  |g 1.  |t Modelling --  |g 2.  |t Temporal Partitioning Algorithms --  |g 3.  |t Conclusion --  |g 5.  |t Temporal Placement --  |g 1.  |t Offline Temporal Placement --  |g 2.  |t Online Temporal Placement --  |g 3.  |t Managing the Device's Free Space with Empty Rectangles --  |g 4. 
505 8 0 |g 8  |t Conclusion. 
650 0 |a Adaptive computing systems 
650 0 |a Field programmable gate arrays 
650 0 |a Programmable array logic 
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650 7 |a Field programmable gate arrays  |2 fast 
650 7 |a Programmable array logic  |2 fast 
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