Cryptographic hardware and embedded systems -- CHES 2005 : 7th international workshop, Edinburgh, UK, August 29-September 1, 2005 : proceedings /
"These are the proceedings of the 7th Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005) held in Edinburgh, Scotland from August 29 to September 1, 2005."
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| Other Authors: | , |
| Format: | Conference Proceeding Book |
| Language: | English |
| Published: |
Berlin ; New York :
Springer,
2005
Berlin ; New York : c2005 Berlin ; New York : ©2005 |
| Series: | Lecture notes in computer science ;
3659 Lecture notes in computer science ; 3659 Lecture notes in computer science 3659 |
| Subjects: |
Table of Contents:
- Resistance of randomized projective coordinates against power analysis / William Dupuy and Sebastien Kunz-Jacques
- Templates as master keys / Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi and Kai Schramm
- A stochastic model for differential side channel cryptanalysis / Werner Schindler, Kerstin Lemke and Christof Paar
- A new baby-step giant-step algorithm and some applications to cryptanalysis / Jean Sebastien Coron, David Lefranc and Guillaume Poupard
- Further hidden Markov model cryptanalysis / P. J. Green, R. Noad and N. P. Smart
- Energy-efficient software implementation of long integer modular arithmetic / Johann Grossschadl, Roberto M. Avanzi, Erkay Savas and Stefan Tillich
- Short memory scalar multiplication on Koblitz curves / Katsuyuki Okeya, Tsuyoshi Takagi and Camille Vuillaume
- Hardware/software co-design for hyperelliptic curve cryptography (HECC) on the 8051 [mu]P / Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel and Ingrid Verbauwhede
- SHARK : a realizable special hardware sieving device for factoring 1024-bit integers / Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata and Colin Stahlke
- Scalable hardware for sparse systems of linear equations, with applications to integer factorization / Willi Geiselmann, Adi Shamir, Rainer Steinwandt and Eran Tromer
- Design of testable random bit generators / Marco Bucci and Raimondo Luzzi
- Successfully attacking masked AES hardware implementations / Stefan Mangard, Norbert Pramstaller and Elisabeth Oswald
- Masked dual-rail pre-charge logic : DPA-resistance without routing constraints / Thomas Popp and Stefan Mangard
- Masking at gate level in the presence of glitches / Wieland Fischer and Berndt M. Gammel
- Bipartite modular multiplication / Marcelo E. Kaihara and Naofumi Takagi
- Fast truncated multiplication for cryptographic applications / Laszlo Hars
- Using an RSA accelerator for modular inversion / Martin Seysen
- Comparison of bit and word level algorithms for evaluating unstructured functions over finite rings / B. Sunar and D. Cyganski
- EM analysis of Rijndael and ECC on a wireless Java-based PDA / Catherine H. Gebotys, Simon Ho and C. C. Tiu
- Security limits for compromising emanations / Markus G. Kuhn
- Security evaluation against electromagnetic analysis at design time / Huiyun Li, A. Theodore Markettos and Simon Moore
- On second-order differential power analysis / Marc Joye, Pascal Paillier and Berry Schoenmakers
- Improved higher-order side-channel attacks with FPGA experiments / Eric Peeters, Francois-Xavier Standaert, Nicolas Donckers and Jean-Jacques Quisquater
- Secure data management in trusted computing / Ulrich Kuhn, Klaus Kursawe, Stefan Lucks, Ahmad-Reza Sadeghi and Christian Stuble
- Data remanence in flash memory devices / Sergei Skorobogatov
- Prototype IC with WDDL and differential routing - DPA resistance assessment / Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont and Ingrid Verbauwhede
- DPA leakage models for CMOS logic circuits / Daisuke Suzuki, Minoru Saeki and Tetsuya Ichikawa
- The "backend duplication" method / Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu and Renaud Pacalet
- Hardware acceleration of the tate pairing in characteristic three / P. Grabher and D. Page
- Efficient hardware for the tate pairing calculation in characteristic three / T. Kerins, W. P. Marnane, E. M. Popovici and P. S. L. M. Barreto
- AES on FPGA from the fastest to the smallest / Tim Good and Mohammed Benaissa
- A very compact S-box for AES / D. Canright